The present invention relates to sampling clock circuits in general, and in particular to a sampling clock control circuit to provide coherent switching between sampling clock rates.
In electronic instruments such as digital processing oscilloscopes and transient digitizing oscilloscopes, high speed analog electrical pulses are converted to digital representations to facilitate storage, analysis, and display. Generally, the conversion to digital representations is accomplished by sampling the analog pulses at a fixed rate and then quantizing the samples by means of an analog-to-digital converter. A sampling clock having a plurality of selectable clock rates may be provided to operate the sampling circuit at different rates for input signals having different frequencies or transition times. This permits faster signals to be sampled at a faster rate, and slower signals at a proportionately slower rate so that a maximum of information may be obtained from the analog signal without exceeding available memory space. However, for wide pulses, where the data changes at high rates on the leading and falling edges and changes very little, if at all, over the flat portions of the pulses, it has heretofore been necessary to operate the sampling clock at the highest expected rate in order to acquire the entire waveform. This results in inefficient use of sampling circuits and memory space for the flat portions of the pulses.
In particular, for radar pulse analysis, it would be desirable to divide the waveform into precise time intervals and sample the data during each interval at a rate commensurate with the expected rate of change of data within each interval. However, switching between clock rates has heretofore been incoherent, which would result in unpredictable time relationships between samples acquired at different rates and thus yield a stored and displayable waveform of arbitrary time dimensions.